The present invention generally relates to a data processing unit having a bypass circuit, and in particular to a data processing unit having a bypass circuit which can cope with a bypass control for various data having different data length (word length) with high flexibility.
Generally, data processing in a data processing unit such as a computer or a microprocessor is carried out with a register file. By using a register file, high-speed data processing can be done without being limited by the access speed of an external memory. However, a delay may occur in data processing even with the register file, because it takes time to renew or rewrite data in the register file.
Referring to FIGS. 1 and 2, a processing block 1 subjects input data Din to a predetermined data processing, and produces output data Dout in a processing cycle 1. The output data Dout is then written into a register file 2. Thereby, the content of the register file is renewed with the output data Dout during a processing cycle 2 shown in FIG. 2. Thereafter, when the next data processing step using the just written data (hatched block inside the Processing cycle 2) is required, necessary data, including the hatched data are read out from the register file 2 in a processing cycle 3, and the desired data processing is carried out. It can be seen from the above-mentioned description that the data processing which uses the data just written (renewed) cannot be performed immediately after the processing cycle 2, or in other words, must be kept waiting during the processing cycle 2. This causes a delay of data processing.
In order to overcome the above-mentioned problem, a bypass control has been proposed. FIG. 3 shows the basic arrangement for a conventional bypass control. As shown, a bypass circuit 3, which is arranged between data buses, functions to pass the processed data Dout derived from the processing block 1 and supply the processing block 1 with the bypassed data Din as it is. When the register file 2 is renewed with the processed data Dout supplied from the processing block 1, which is to be used in the next data processing, the processed data Dout is passed through the bypass circuit 3 and is directly supplied, as the input data Din, to the processing block 1. Then, the processing block 1 carried out the next data processing by referring to the bypassed input data. In this manner, the bypass circuit 3 makes it possible to perform both the next data processing and renewal of the register file 2 at the same time.
FIG. 4 illustrates a procedure of the above-mentioned data processing. It can be seen from FIG. 4 that the first data processing operation and the following data processing operation can be carried out in successive processing cycles 1 and 2.
However, in the conventional bypass control, the register file 2 and the bypass circuit 3 are designed so as to conform to a large-scale computer designed to process data having a specific (fixed) word length. For this reason, the structure of FIG. 3 is not suitable for a small-scale computer where word length of data is not fixed but variable.
FIG. 5 is a view illustrating the above-mentioned problem. It is assumed in FIG. 5 that a data processing is performed on low-order bytes of word length data D1 and D2 stored in the register file 2. The low-order byte of a word length data in the register file 2 is reversed with a resultant data R, and a revised word-length data D3 including the data R is used in the next data processing. In this case, only the data R is allowed to pass through the bypass circuit 3, while the high-order byte of the data D3 is still placed in the register file 2. Therefore, at this time, the processing block 1 cannot refer to the word length of data. For this reason, in practical use, after the renewal of the register file 2 ends, the word-length data having the revised low-order byte R in the register file 2 is read out therefrom and used in the next data processing step. The result is a loss of the advantages provided by the bypass control: a delay of data processing cannot be effectively overcome even when the bypass control is employed.